Artificial intelligence (AI) data centers are preparing to shift from 48-volt to 800-volt direct current (DC) as chips draw more electricity.
Higher voltage cuts the current needed for the same power, saving copper, energy and floor space. Solid-state transformers (SSTs) built on silicon carbide (SiC) chips are emerging as the equipment to make the jump, replacing several conversion stages with just one.
“The power requirement in AI data centers keeps going up, and because it’s going up, there has already been a migration from 12 volts to 48 volts,” said Ingo Lüdtke, head of power electronics at Semiconductor Catapult. “Now with the advent of the massive use of AI, there is a call for increasing to 800 volts.”
“When increasing the voltage, the current in the supply reduces proportionally. For a 100 kilowatt supply, instead of using over 2,000 amps, what is required is only 125 amps,” he said. “Ultimately that massive reduction saves a lot of copper in AI data centers.”
The move from 48V to 800V cuts current by a factor of about 17. Lüdtke said it also reduces transmission losses inside the data center and shrinks the space taken by power conversion equipment.
Efficiency is not the only reason for the change.
“The loads in AI data centers are very specific in that they can operate in a synchronized way, and when they do, the power can fluctuate massively,” he said. “So the system to be designed also needs to have a very high dynamic response.”
One of his slides contrasted the steady, grid-friendly load of traditional processors with the microsecond spikes and voltage sags of AI chips, which stress the grid and risk throttling.
Semiconductor Catapult, a not-for-profit research center set up by Innovate UK in 2018, relaunched under its new name on September 29 following the government’s AI Hardware Plan. Formerly the Compound Semiconductor Applications (CSA) Catapult, it now focuses on energy-efficient hardware for AI data centers and defense.
One step from grid
Lüdtke’s talk, “Silicon Carbide for AI Data Centres: Enabling Next-Generation Solid-State Transformers,” took place on the Semiconductors UK stage at Microelectronics UK 2026, held in London on September 29 and organized by IQPC Exhibitions.
He has led the Catapult’s power electronics team since 2018 and is an honorary visiting professor at Cardiff University.
The Catapult’s earlier Project ELIPS represents today’s AI racks, converting a three-phase 415V supply into 48V DC with a 1.2-kilovolt (kV) SiC rectifier and an 80-kilowatt (kW) shelf of eight 10kW power units. The team is now reworking it to take 11kV in and deliver 800V out.
Power in today’s AI data centers typically passes through a chain of five conversion stages before it reaches a chip:
A 50Hz transformer steps an 11kV supply down to 415 volts alternating current (AC)
An uninterruptible power supply (UPS) converts AC to DC for its batteries and back to AC
A rectifier turns that into 48V DC
A DC-DC converter steps it down to 12V
A point-of-load converter delivers around 1V to the graphics processing units (GPUs)
“The new system can move from 11 kilovolts AC in one conversion step to 800 volt DC, and that tidies up a lot of the infrastructure in AI data centers,” Lüdtke said. “It reduces the footprint and increases the efficiency ultimately because there are fewer conversion stages to go through.”
In the layout on his slide, a SiC SST sits in a “sidecar” beside the IT rack and handles medium-voltage conversion, isolation and two-way power flow. Inside the rack, a DC-DC stage drops 800V to 6V before vertical power delivery feeds the GPU.
Lüdtke said the industry now has a clear direction for that equipment.
In June, the Open Compute Project (OCP), an industry group of hyperscalers and their hardware suppliers, published its first SST specification. Version 0.3, credited to Google, Microsoft and Nvidia, calls for:
A 13.8kV or 34.5kV medium-voltage input suited to the US grid
5 megawatts (MW) or 10MW of DC output
An 800V DC bus
At least 98% efficiency from half to full load
Tolerance of a 150% overload for 150 milliseconds
The Catapult translated the specification for Britain’s 11kV, three-wire grid supply and chose a 1MW building block, with its 800V output feeding the OCP bus directly.
“We believe that a larger 5 or 10 megawatt system can be built up from one megawatt, and it can also be used in a rack system right next to the computing at only one megawatt,” he said.
The die-count problem
Higher-voltage SiC chips open the door to simpler circuit designs, such as a matrix SST built with 10kV devices, and to bidirectional designs that need fewer switches.
“Despite some of these schematic diagrams looking a lot simpler, they are in fact not simpler when you consider that when the voltage rating is increasing, the maximum current rating per die massively decreases,” Lüdtke said. “It’s not so easy to just say higher voltage simplifies. We also need to consider how many parallel devices are needed.”
The highest-current bare SiC dies shown on his slide fell from 202 amps at 1.2kV to 52 amps at 3.3kV and 20 amps at 10kV. Higher-rated dies need fewer devices stacked in series, but more in parallel to carry the current.
On a 33kV grid, each switch position needs 31 dies rated at 1.2kV in series, or just four at 10kV.
The Catapult screened several circuit layouts for a 1MW, 800V block on the UK supply, applying the same die-count rules and loss models to each. The goal was to use the fewest dies while maximizing efficiency.
In every layout tested, 3.3kV SiC delivered the highest efficiency, including the input-series output-parallel (ISOP) design some manufacturers already use.
“That’s a good conclusion, but it still requires 288 dies to be used in the system. So that’s going to be expensive,” he said.
A monolithic design needed 432 dies. A modular bridge rectifier matched the reference design’s 288 dies and led every voltage class on efficiency, reaching a projected 98.54% at full load with 3.3kV devices. Lüdtke said its extra magnetic coupling also helps with fault handling.
Moving to 10kV devices would cut the die count further, but at a cost in efficiency.
The study also found that conduction losses dominate, so each new SiC generation with lower on-resistance feeds directly into better system results.
“Ultimately this is what’s called a multi-objective optimization problem, where power converter design is very much merged with power system design because so many power converters are used in the same topology,” he said.
The Catapult describes the results as initial simulations and says detailed circuit models are needed to verify them.